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rev. 0.6 6/07 copyright ? 2007 by silicon laboratories si552 d ual f requency v oltage -c ontrolled c rystal o scillator (vcxo) 10 mh z to 1.4 gh z features applications description the si552 dual-frequency vcxo utilizes silicon laboratories? advanced dspll ? circuitry to provide a very low jitter clock for all output frequencies. the si552 is available with any-rate output frequency from 10 to 945 mhz and selected frequencies to 1400 mhz. unlike traditional vcxos, where a different crystal is required for each output frequency, the si552 uses one fixed crystal frequency to provide a wide range of output frequencies. this ic-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. the si552 ic-based vcxo is factory-configurable for a wide variety of user specifications including frequency, supply voltage, output format, tuning slope, and temperature stability. specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. functional block diagram available with any-rate output frequencies from 10?945 mhz and selected frequencies to 1.4 ghz two selectable output frequencies 3rd generation dspll ? with superior jitter performance 3x better frequency stability than saw-based oscillators internal fixed crystal frequency ensures high reliability and low aging available cmos, lvpecl, lvds, and cml outputs 3.3, 2.5, and 1.8 v supply options industry-standard 5 x 7 mm package and pinout pb-free/rohs-compliant sonet/sdh xdsl 10 gbe lan/wan low-jitter clock generation optical modules clock and data recovery fixed frequency xo any-rate 10?1400 mhz dspll ? clock synthesis v dd clk+ clk- v c gnd fs adc ordering information: see page 8. pin assignments: see page 7. (top view) si5602 1 2 3 6 5 4 v c gnd fs v dd clk+ clk? si552 r evision d
si552 2 rev. 0.6 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled lvpecl cml lvds cmos ? ? ? ? 120 108 99 90 130 117 108 98 ma tristate mode ? 60 75 frequency select (fs) 2 v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section 3. "ordering information" on page 8 for further details. 2. fs pin includes a 17 k ? resistor to vdd. table 2. v c control voltage input parameter symbol test condition min typ max units control voltage tuning slope 1,2,3 k v 10 to 90% of v dd ?33 45 90 135 180 356 ? ppm/v control voltage linearity 4 l vc bsl ?5 1 +5 % incremental ?10 5 +10 modulation bandwidth bw 9.3 10.0 10.7 khz v c input impedance z vc 500 ? ? k ? nominal control voltage v cnom @ f o ?v dd /2 ? v control voltage tuning range v c 0v dd v notes: 1. positive slope; selectable option by part number . see section 3. "ordering information" on page 8. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. k v variation is 10% of typical values. 4. bsl determined from deviation from best straight line fit with v c ranging from 10 to 90% of v dd . incremental slope determined with v c ranging from 10 to 90% of v dd .
si552 rev. 0.6 3 table 3. clk output frequency characteristics parameter symbol test condition min typ max units nominal frequency 1,2,3 f o lvds/cml/lvpecl 10 ? 945 mhz cmos 10 ? 160 temperature stability 1,4 t a = ?40 to +85 c ?20 ?50 ?100 ? ? ? +20 +50 +100 ppm absolute pull range 1,4 apr 25 ? 375 ppm aging frequency drift over first year. ? ? 3 ppm frequency drift over 15 year life. ? ? 10 power up time 5 t osc ??10ms settling time after fs change t frq ??10ms notes: 1. see section 3. "ordering information" on page 8 for further details. 2. specified at time of order by part number. also available in frequencies from 970 to 1134 mhz and 1213 to 1417 mhz. 3. nominal output frequency set by v cnom =v dd /2. 4. selectable parameter specified by part number. 5. time from power up or tristate mode to f o (to within 1 ppm of f o ). table 4. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.55 ? 0.95 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.5 0.7 0.9 v pp cml output option 2 v o mid-level ? v dd ? 0.75 ? v v od swing (diff) 0.70 0.95 1.20 v pp cmos output option 3 v oh i oh =32ma 0.8 x v dd ? v dd v v ol i ol =32ma ? ? 0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with c l =15pf ? 1 ? ns symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term = 100 ? (differential). 3. c l = 15 pf
si552 4 rev. 0.6 table 5. clk output phase jitter parameter symbol test condition min typ max units phase jitter (rms) 1,2,3 for f out > 500 mhz j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.26 0.26 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.27 0.26 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.32 0.26 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.40 0.27 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.49 0.28 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.87 0.33 ? ? notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performanc e, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions.
si552 rev. 0.6 5 phase jitter (rms) 1,2,3 for f out of 125 to 500 mhz j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.43 0.34 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.50 0.34 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.59 0.35 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 1.00 0.39 ? ? table 6. clk output period jitter parameter symbol test condition min typ max units period jitter* j per rms ? 2 ? ps peak-to-peak ? 14 ? *note: any output mode, incl uding cmos, lvpecl, lvds, cml. n = 1000 cycles . refer to an279 fo r further information. table 5. clk output phase jitter (continued) parameter symbol test condition min typ max units notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performanc e, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions.
si552 6 rev. 0.6 table 7. clk output phase noise (typical) offset frequency 74.25 mhz 90 ppm/v lvpecl 491.52 mhz 45 ppm/v lvpecl 622.08 mhz 135 ppm/v lvpecl units 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz ?87 ?114 ?132 ?142 ?148 ?150 n/a ?75 ?100 ?116 ?124 ?135 ?146 ?147 ?65 ?90 ?109 ?121 ?134 ?146 ?147 dbc/hz table 8. absolute maximum ratings 1 parameter symbol rating units maximum operating temperature t amax 85 oc supply voltage v dd ?0.5 to +3.8 volts input voltage (any input pin) v i ?0.5 to v dd + 0.3 volts storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd 2500 volts soldering temperature (pb-free profile) 2 t peak 260 oc soldering temperature time @ t peak (pb-free profile) 2 t p 20?40 seconds notes: 1. stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. functional operation or specification co mpliance is not implied at these conditions. exposure to maximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c. refer to si5xx packaging faq available for download from www.silabs.com/vcxo for further information, including soldering profiles. table 9. environmental compliance the si552 meets the following qualification test requirements. parameter conditions/test method mechanical shock mil-std-883f, method 2002.3 b mechanical vibration mil-std-883f, method 2007.3 a solderability mil-std-8 83f, method 203.8 gross & fine leak mil-std-883f, method 1014.7 resistance to solvents mil-std-883f, method 2016
si552 rev. 0.6 7 2. pin descriptions table 10. si552 pin descriptions pin name type function 1 v c analog input control voltage 2 fs* input frequency select: 0 = first frequency selected 1 = second frequency selected 3 gnd ground electrical and case ground 4 clk+ output oscillator output 5 clk? (n/a for cmos) output complementary output (n/c for cmos) 6 v dd power power supply voltage *note: fs includes a 17 k ? pullup resistor to v dd . see section 3. "ordering information" on page 8 for details on frequency select and oe polarity ordering options. 1 2 3 6 5 4 v c gnd fs v dd clk+ clk? (top view)
si552 8 rev. 0.6 3. ordering information the si552 supports a variety of options including fr equency, temper ature stability, tuning sl ope, output format, and v dd . specific device configurations are programmed into the si552 at time of sh ipment. configurations are specified using the part number configuration chart show n below. silicon labs provides a web browser-based part number configuration utility to simplify this process. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the si552 vcxo series is supplied in an industry -standard, rohs-compliant, lead-free, 6-pad, 5 x 7 mm package. tape and reel packaging is an ordering option. figure 1. part number convention dd r = tape & reel blank = trays operating temp range (c) g ?40 to +85 c device revision letter 552 dual vcxo product family 1 st option code code vdd output format a 3.3 lvpecl b3.3lvds c3.3cmos d3.3cml e 2.5 lvpecl f2.5lvds g2.5cmos h2.5cml j1.8cmos k1.8cml notes : cmos available to 160 mhz. 552 x x xxxxxx d g r 2 nd option code temperature tuning slope minimum apr stability kv (ppm) for vdd @ code ppm (max) ppm/v (typ) 3.3 v 2.5 v 1.8 v a 100 180 100 75 25 b 100 90 30 note 6 note 6 c 50 180 150 125 75 d50 90 803025 e 20 45 25 note 6 note 6 f 50 135 100 75 50 g 20 356 375 300 235 h 20 180 185 145 105 j 20 135 130 104 70 k 100 356 295 220 155 m 20 33 12 note 6 note 6 notes: 1. for best jitter and phase noise performance, always choose the smallest kv that meets the application?s minimum apr requirements. unlike saw-based solutions which require higher higher kv values to account for their higher temperature dependence, the si55x series provides lower kv options to minimize noise coupling and jitter in real- world pll designs. see an255 and an266 for more information. 2. apr is the ability of a vcxo to track a signal over the product lifetime. a vcxo with an apr of 25 ppm is able to lock to a clock with a 25 ppm stability over 15 years over all operating conditions. 3. nominal pull range () = 0.5 x v dd x tuning slope. 4. nominal absolute pull range ( apr) = pull range ? stability ? lifetime aging = 0.5 x v dd x tuning slope ? stability ? 10 ppm 5. minimum apr values noted above include worst case values for all parameters. 6. combination not available. example part number: 552af000108dgr is a 5x7mm dual vcxo in a 6 pad package. since the six digit code (000108) is > 000100, f0 is 644.53125 mhz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3v supply and lvpecl output. temperature stability is specified as 50 ppm and the tuning slope is 135 ppm/v. the part is specified for a -40 to +85 c am bient temperature range operation and is shipped in tape and reel format. 6-digit frequency designator code two unique frequencies can be specified within the following bands of frequencies: 10 to 945 mhz, 970 to 1134 mhz, and 1213 to 1417 mhz. a six digit code will be assigned for the specified combination of frequencies. codes > 000100 refer to dual xos programmed with the lower frequency value selected when fs = 0, and the higher value when fs = 1. six digit codes < 000100 refer to dual xos programmed with the higher frequency value selected when fs = 0, and the lower value when fs = 1.
si552 rev. 0.6 9 4. si55x mark specification figure 2 illustrates the mark specification for the si552. table 11 lists the line information. figure 2. mark specification table 11. si55x top mark description line position description 1 1?10 ?silabs?+ part family number, 5xx (first 3 characters in part number) 2 1?10 si550: option1+option2+freq(7)+temp si552, si554, si550 w/ 8-digit resolu tion: option1+option2+confignum(6)+temp 3 trace code position 1 pin 1 orientation mark (dot) position 2 product revision (d) position 3?6 tiny trace code (4 alphanumeric charac ters per assembly release instructions) position 7 year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) position 8?9 calendar work week number (1?53), to be assigned by assembly site position 10 ?+? to indicate pb-free and rohs-compliant silabs 123 123 4 5 6 r t t t t y w w + 1 2 3 4 5 6 7 8 9 0
si552 10 rev. 0.6 5. outline diagram and suggested pad layout figure 3 illustrates the package details for the si552. table 12 lists the val ues for the dimensions shown in the illustration. figure 3. si552 outline diagram table 12. package diagram dimensions (mm) dimension min nom max a 1.45 1.65 1.85 b1.21.41.6 c0.60 typ d 7.00 bsc d1 6.10 6.2 6.30 e 2.54 bsc e 5.00 bsc e1 4.30 4.40 4.50 l 1.07 1.27 1.47 s 1.815 bsc r 0.7 ref aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10
si552 rev. 0.6 11 6. 6-pin pcb land pattern figure 4 illustrates the 6-pin pcb land pa ttern for the si552. table 13 lists th e values for the dimensions shown in the illustration. figure 4. si552 pcb land pattern table 13. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref e 2.54 bsc e2 4.15 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1.70 typ y2.15 ref zd ? 6.78 ze ? 6.30 notes: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design based on ipc-7351 guidelines. 3. all dimensions shown are at ma ximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
si552 12 rev. 0.6 d ocument c hange l ist revision 0.3 to revision 0.4 updated table 1, ?recommended operating conditions,? on page 2. added maximum supply current specifications. specified relationship between temperature at startup and operation temperature. revision 0.4 to revision 0.5 updated note 3 in table 1, ?recommended operating conditions,? on page 2. revision 0.5 to revision 0.6 updated table 1, ?recommended operating conditions,? on page 2. device maintains stable operation over ?40 to +85 oc operating temperature range. supply current specifications updated for revision d. updated table 4, ?clk output levels and symmetry,? on page 3. updated lvds differential peak-peak swing specifications. updated table 5, ?clk output phase jitter,? on page 4. updated table 6, ?clk outp ut period jitter,? on page 5. revised period jitter specifications. updated table 8, ?absolute maximum ratings 1 ,? on page 6 to reflect the soldering temperature time at 260 oc is 20?40 sec per jedec j-std-020c. updated 3. "ordering information" on page 8. changed ordering instructions to revision d. added 4. "si55x mark specification" on page 9.
si552 rev. 0.6 13 n otes :
si552 14 rev. 0.6 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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